The present invention relates to a switching circuit and a charge transfer device using such a circuit in a portion of its output circuit.
FIG. 17 shows a structure of a solid-state image sensing apparatus such as a CCD linear sensor, and FIG. 18 shows a structure of the periphery of a charge voltage converter. First, a CCD linear sensor 170 comprises a sensor row 172 consisting of a multiplicity of sensor elements 171 (corresponding to, e.g., 2000 pixels) which are arrayed in a row to convert incident light into a signal charge of an amount proportional to the light quantity and store the signal charge therein, a read gate 173 for reading out the signal charge stored in each of the sensor elements 171 of the sensor row 172, and a charge transfer register 174 consisting of CCDs to unidirectionally transfer the signal charge read out by the read gate 173. The charge transfer register 174 is equipped with, at an end thereof, a charge-voltage converter 175 for detecting the transferred signal charge and converting such charge into a proportional voltage.
The read gate 173 is driven by a read gate pulse .o slashed.ROG applied thereto via a terminal 176. The charge transfer register 174 is driven by two-phase driving pulses .o slashed.1 and .o slashed.2 generated by a timing generator circuit 177 and applied via a driver 178. The charge-voltage converter 175 is reset by a reset pulse .o slashed.rs generated similarly by the timing generator circuit 177 and applied via the driver 178. The timing generator circuit 177 generates various timing signals, such as two-phase driving pulses .o slashed.1, .o slashed.2 and a reset pulse .o slashed.rs, in response to clock pulses .o slashed.CLK inputted thereto via a terminal 179. An output voltage V.sub.fd from the charge-voltage converter 175 is first supplied to a buffer 181 and then is delivered therefrom as a CCD output voltage V.sub.out via an output terminal 181. Subsequently the voltage V.sub.out is converted into a digital signal by an AD converter 182 in accordance with an AD timing pulse.
In FIG. 18, the charge-voltage converter 175 is constructed as a floating diffusion amplifier which consists of a floating diffusion (FD) 184 composed of N+ type impurity and formed adjacently to the output gate 183 which is composed of N- type impurity and constitutes the final stage of the charge transfer register 174, a reset drain (RD) 185 composed of N+ type impurity and formed via a channel region of N type impurity, and a reset gate (RG) 186 disposed above the channel region, wherein the signal charge transferred from the output gate 183 to the floating diffusion 184 is converted into a voltage V.sub.fd and then is outputted. A predetermined voltage (e.g., supply voltage V.sub.dd) is applied as a reset drain voltage V.sub.rd to the reset drain 185. Meanwhile the aforementioned reset pulse .o slashed.rs is applied to the reset gate 186.
FIG. 19 shows a general output waveform of the CCD output voltage V.sub.out obtained when none of sample and hold action (S/H) is performed in the buffer 180. As obvious from this output waveform, when a reset pulse .o slashed.rs applied to the reset gate 186 is turned off, there occurs a .o slashed.rs coupling which signifies a potential variation caused in the floating diffusion 184 due to capacitive coupling derived from a parasitic capacitance between the reset drain 185 and the reset gate 186. Supposing now that the CCD output voltage V.sub.out has an amplitude of 1V.sub.p--p, if the .o slashed.rs coupling is 0.5V, it follows that a voltage of 1.5V or more needs to be ensured for the operating region of the output circuit in consideration of some amplitude variation of the .o slashed.rs coupling (derived from variations in manufacture and ambient environment in use). In view of the above situation, it is essential to reduce the .o slashed.rs coupling for facilitating design of the output circuit.
FIG. 20 shows an output waveform of the CCD output voltage V.sub.out obtained when a sample holding action is performed in the buffer 180. Although the entire amplitude of the CCD output voltage V.sub.out is also reduced by such a sample holding action, it becomes necessary to take the .o slashed.rs coupling into consideration in designing a front stage 187 of the sample hold circuit 186 (consisting of two source-follower stages in this example), as obvious from the circuit diagram of FIG. 18. Further when CDS (correlated double sampling) or the like is to be executed for elimination of noise, the circuit configuration anterior to the sample hold circuit 186 is complicated since such CDS needs to be performed prior to the sample holding action. And the more complicate the circuit configuration is rendered, there exist greater difficulties in designing a large operating region.
Another problem existing with regard to the .o slashed.rs coupling relates to noise. One of noises included in the CCD output voltage V.sub.out is random noise which is termed reset noise in a broad sense. The reset noise is classified into resistance noise in its narrow sense, distribution noise caused when the charge under the gate is distributed to the floating diffusion at turn-off of the reset gate 186, and coupling noise caused by variation of the .o slashed.rs coupling derived from capacitive coupling. Here, distribution noise and coupling noise are dependent on the reset pulse .o slashed.rs.
The distribution noise raises a problem relative to distribution of the charge on a channel or to a transfer time to the drain at (or immediately after) turn-off of a transistor (MOS transistor consisting of floating diffusion 184, reset drain 185 and reset gate 186) in the reset gate. If the mutual conductance g.sub.m of the MOS transistor is sufficiently high, the distribution noise changes depending on its turn-off speed. And this noise becomes larger in accordance with increase of the speed. The speed is determined on the basis of the value obtained by dividing the amplitude of the .o slashed.rs coupling by the fall time of the reset pulse .o slashed.rs.
As for the coupling noise, some influence is derived from the impedance due to wiring and so forth to the reset drain 185 supplied normally with the source voltage V.sub.dd and also from the MOS transistor in the reset gate, and the coupling noise is dependent on the fall speed of the rest pulse .o slashed.rs. More specifically, when the impedance is high, the coupling is increased by the parasitic capacitance between the reset drain 185 and the reset gate 186, whereby the noise is also increased. To the contrary, when the fall speed of the reset pulse .o slashed.rs is low, the coupling is reduced by the influence from the impedance and the MOS transistor in the reset gate. To realize reduction of the coupling itself is significant in view of both design and performance, as described.
For reduction of the coupling, there are the following means. First, FIG. 21 is a circuit diagram of a fundamental .o slashed.rs driver. This .o slashed.rs driver comprises a first-stage C-MOS inverter 211 consisting of a P-MOS transistor M1 and an N-MOS transistor M2 connected between a power supply V.sub.dd and the ground, a second-stage C-MOS inverter 212 consisting of a P-MOS transistor M3 and an N-MOS transistor M4 connected between the power supply V.sub.dd and the ground similarly to the above, and a load capacitor CL connected between an output line 213 and the ground. In contrast with the .o slashed.rs driver having such a circuit configuration, the present example is so contrived as shown in FIG. 22 for realizing reduction of the coupling, wherein the source of an N-MOS transistor M4 in a second-stage C-MOS inverter 212 is connected to a power supply V.sub.cc. The output voltage of this power supply V.sub.cc is intermediate between the voltage of the power supply V.sub.dd and the ground level.
FIGS. 23A and 23B show waveforms of reset pulses .o slashed.rs and CCD outputs V.sub.out, respectively, in the circuit examples 1 and 2 of FIGS. 21 and 22. And FIG. 24 shows cross-section potentials in the vicinity of a floating diffusion (FD) at time points t1, t2 and t3 in FIGS. 23A and 23B. According to the circuit example 2 of FIG. 22, the low level of the reset pulse .o slashed.rs is set to be higher than that in the circuit example 1 of FIG. 21 as denoted by a single-dot chained line in FIG. 23A, so that the amplitude of the reset pulse .o slashed.rs itself can be diminished, whereby the coupling to the output V.sub.fd of the floating diffusion is also reducible correspondingly thereto, as obvious from FIG. 23B. However, if the amplitude of the reset pulse .o slashed.rs is diminished extremely, it becomes impossible to sufficiently ensure the dynamic range of the floating diffusion. Therefore, in the related art mentioned above, there exists some restriction in diminishing the amplitude of the reset pulse .o slashed.rs to a certain degree to consequently limit the reduction of the coupling as well.